1. Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly to a differential logic circuit using the effect of a capacitor coupling and a high-speed sense amplifier to achieve the advantage of high-speed transmission and low power consumption.
2. Description of the Prior Art
It is a design trend to use differential logic circuits for general CMOS (Complementary Metal Oxide Semiconductor) design. However, the switching probability is 1 when the dynamic differential circuit is used, thereby resulting in higher power consumption.
For instance, U.S. Pat. No. 4,570,084 discloses a differential logic circuit controlled by a clock pulse. When the clock pulse is 0, the-output differential pair is preset to a predetermined voltage (for example, 0V). When the clock pulse is 1, evaluation starts and the output differential pair is set to the corresponding differential mode using the complementary characteristic of two complementary logic gate circuits (i.e., one is xe2x80x9c1xe2x80x9d, the other is xe2x80x9c0xe2x80x9d). This differential logic circuit is commonly used. The common operation mode of logic circuits is used in U.S. Pat. No. 4,570,084, wherein the differential logic signal must satisfy the corresponding voltage level to attain the correct result.
However, the differential logic signal itself need not attain the full amplitude for the corresponding logic value to be identified. As long as there is fixed voltage difference between two signals, it can be quickly amplified to the corresponding level. For instance, U.S. Pat. No. 4,843,264 discloses a sense amplifier which uses a cross-coupled circuit to amplify the small voltage difference (for example, 100 mV) between the input signals. Therefore, a small voltage difference can be amplified to a differential logic signal of normal level. Furthermore, U.S. Pat. No. 4,910,713 discloses another similar sense amplifier. The use of a sense amplifier to process differential logic signals allows a corresponding logic level to be quickly generated from a small voltage difference while reducing the power consumption.
From the above, the main object of the present invention is to provide a differential logic circuit-which uses a sense amplifier to process the differential output signal of the differential logic circuit and uses the effect of a capacitor coupling to achieve high-speed transmission and low power consumption.
From this, the main object of the present invention is to provide a capacitor-coupling differential logic circuit which uses the effect of a coupling capacitor pair (the first capacitor and the second capacitor) and sense amplifier to process the output of the differential circuit. In the differential circuit, there is at least an external input terminal and a pair of internal differential terminals, wherein the external input terminal is used to receive input signal. The first capacitor is connected to the control signal Ø2 at one end and is connected to the first internal differential terminal of the internal differential terminal pair at the other end. The second capacitor is connected to the control signal Ø2 at one end and the second internal differential terminal of the internal differential terminal pair at the other end. The control signal Ø2 can be a pulse. The first capacitor and the second capacitor can couple the control signal Ø2 to the corresponding internal differential terminal pair. For example, when the control signal Ø2 is at logic xe2x80x9c1xe2x80x9d, the internal differential terminal pair preset to xe2x80x9c0xe2x80x9d can be coupled to a higher voltage state. When differential circuit evaluates, a voltage difference is generated on the internal signal of the internal differential terminal pair according to the input signal. The input terminal pair of the sense amplifier is connected to the internal differential terminal pair to amplify the internal signal voltage difference of the internal differential terminal pair and output it to the output terminal pair of the sense amplifier.
Furthermore, the present invention also provides a second capacitor coupling differential logic circuit, the difference between this circuit and the above circuit is that the coupling capacitor pair is simplified and parasitic capacitors are used instead. In the differential circuit of this embodiment, there is at least an external input terminal and an internal differential terminal pair, wherein the external input terminal is used to receive input signal and the input terminal pair of the sense amplifier is connected to the internal differential terminal pair to amplify the internal signal of the internal differential terminal pair and output it to the output terminal pair of the sense amplifier. The gates of the first input transistor and the second input transistor in the sense amplifier correspond to the input terminal pair of the sense amplifier, respectively. There is parasitic capacitance between the gate and the source of the corresponding transistor. The effect of the parasitic capacitance here is similar to that of the coupling capacitance above. There is a control transistor in the sense amplifier, the source of which is connected to the sources of the first input transistor and the second input transistor, and the drain of which is connected to a predetermined voltage. Thus, the parasitic capacitance can couple the predetermined voltage to the internal differential terminal pair when the control transistor conducts. The differential circuit can generate a voltage difference on internal signal at internal differential terminal pair according to the input signal. The sense amplifier then amplifies this voltage difference and generates the corresponding differential signal under fast and low power consumption condition.